A preliminary model for lot sizing In semiconductor manufacturing

In this paper, we develop a preliminary math­ ematical model for determining lot sizes for a single product which has several quality levels. The qual­ ity level of each unit is determined ("binned") by testing the product after it is produced. Binning based on performance after production is common in several industries, but the application which motivated the model developed here is semicon­ ductor manufacture. A typical example is a micro­ processor that operates at one of several different speeds. Specifically, consider the 80486 micro­ processor developed by Intel Corporation of Santa Clara, California. {The 486 chip is currently the processor of choice for IBM compatible personal computers). At the current time, the 486 operates at three speeds: 25,33 and 50 MHz. The production process is exactly the same in each case. After the chip is produced, it is tested and binned based on its performance. The issue that we address in this paper is to determine the value of the lot size (x) so that we are guaranteed with specified probabilities that the de­ mands for the various grades of product are satis­ fied. We also assume, as is often done for problems of this type, that we may substitute higher quality products for ones of lower quality, but not vice versa. While several related studies have addressed similar issues in more general settings, our ap­ proach will yield a solution which is easy to com­ pute and easy to implement.